Implementation of Efficient Multiplier for High Speed Applications Using FPGA

Multiplication is a predominant operation in many DSP applications. Area and delay are enormous in the multiplication operations, so the high-speed multiplier with a compromised area is required. This paper submits an efficient implementation of high-speed multiplier using a mixed between Vedic mathematics and high-speed adder like Carry Save Adder (CSA). CSA is convenient in adding three numbers and sutra of Vedic mathematics called Urdhva Tiryakbhyam is very suitable for multiplication. Starting with a 2-bit Vedic multiplier, we can be ascending to implement a 64-bit multiplier. After comparison, the obtained result from the proposed multiplier is better than the references in terms of area and delay. All algorithms are coded in VIIDI, and targeted to implement on Virtex-5 and Virtex-6 FPGA kit with ISE 14.5, the simulated results are acquired by Modelsim I0.3d.