On the inherent space complexity of fast parallel multipliers for GF(2m)

被引：12

作者：

Elia, M

Leone, M

机构：

[1] Politecn Torino, Dipartimento Elettron, I-10129 Turin, Italy

[2] TILAB Telecom Italia Lab, I-10148 Turin, Italy

来源：

IEEE TRANSACTIONS ON COMPUTERS | 2002年 / 51卷 / 03期

关键词：

finite fields; parallel multiplier; optimal normal basis;

D O I：

10.1109/12.990131

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A lower bound to the number of AND gates used in parallel multipliers for GF((2M)) under the condition that time complexity be minimum, is determined, In particular, the exact minimum number of AND gates for Primitive Normal Bases and Optimal Normal Bases of Type 11 multipliers is evaluated, This result indirectly suggests that space complexity is essentially a quadratic function of m when time complexity is kept minimum.

引用

页码：346 / 351

页数：6

共 50 条

[21] Fast Parallel GF(2m) Polynomial Multiplication for All Degrees
Cilardo, Alessandro
IEEE TRANSACTIONS ON COMPUTERS, 2013, 62 (05) : 929 - 943
[22] Low complexity multiplexer-based parallel multiplier of GF(2m)
Byun, GY
Kim, HS
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2003, E86D (12) : 2684 - 2690
[23] Low-complexity modified Mastrovito multipliers over finite fields GF(2M)
Song, LL
Parhi, KK
ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI, 1999, : 508 - 512
[24] Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of GF(2m)
Talapatra, Somsubhra
Rahaman, Hafizur
Mathew, Jimson
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2010, 18 (05) : 847 - 852
[25] Subquadratic space complexity Gaussian normal basis multipliers over GF(2m) based on Dickson-Karatsuba decomposition
Pan, Jeng-Shyang
Lee, Chiou-Yng
Li, Yao
IET CIRCUITS DEVICES & SYSTEMS, 2015, 9 (05) : 336 - 342
[26] Multiplexer-based bit-parallel systolic multipliers over GF(2m)
Lee, Chiou-Yng
COMPUTERS & ELECTRICAL ENGINEERING, 2008, 34 (05) : 392 - 405
[27] Efficient testable bit parallel multipliers over GF(2m) with constant test set
Mathew, J.
Rahaman, H.
Pradhan, D. K.
13TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM PROCEEDINGS, 2007, : 207 - +
[28] High-speed bit-parallel systolic multipliers for a class of GF(2m)
Lee, CY
Lu, EH
Jau-Yien
2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS, 2001, : 291 - 294
[29] Derivation of reduced test vectors for bit-parallel multipliers over GF(2m)
Rahaman, H.
Mathew, J.
Pradhan, D. K.
Jabir, A. M.
IEEE TRANSACTIONS ON COMPUTERS, 2008, 57 (09) : 1289 - 1294
[30] Ringed bit-parallel systolic multipliers over a class of fields GF(2m)
Ting, YR
Lu, EH
Lu, YC
INTEGRATION-THE VLSI JOURNAL, 2005, 38 (04) : 571 - 578

← 1 2 3 4 5 →