Power supply noise and logic error probability

被引：2

作者：

Andrade, Dennis ^{[1
]}

Martorell, Ferran ^{[1
]}

Pons, Marc ^{[1
]}

Moll, Francesc ^{[1
]}

Rubio, Antonio ^{[1
]}

机构：

[1] Tech Univ Catalonia UPC, Dept Elect Engn, Barcelona, Spain

来源：

2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3 | 2007年

关键词：

D O I：

10.1109/ECCTD.2007.4529559

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Voltage fluctuations caused by parasitic impedances in the power supply rails of modern ICs are a major concern in nowadays ICs. The voltage fluctuations are spread out to the diverse nodes of the internal sections causing two effects: a degradation of performances mainly impacting gate delays and a noisy contamination of the quiescent levels of the logic that drives the node. Both effects are presented together, in this paper, showing than both are a cause of errors in modern and future digital circuits. The paper groups both error mechanisms and shows how the global error rate is related with the voltage deviation and the period of the clock of the digital system.

引用

页码：152 / 155

页数：4

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