Power supply noise and logic error probability

被引:2
|
作者
Andrade, Dennis [1 ]
Martorell, Ferran [1 ]
Pons, Marc [1 ]
Moll, Francesc [1 ]
Rubio, Antonio [1 ]
机构
[1] Tech Univ Catalonia UPC, Dept Elect Engn, Barcelona, Spain
关键词
D O I
10.1109/ECCTD.2007.4529559
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Voltage fluctuations caused by parasitic impedances in the power supply rails of modern ICs are a major concern in nowadays ICs. The voltage fluctuations are spread out to the diverse nodes of the internal sections causing two effects: a degradation of performances mainly impacting gate delays and a noisy contamination of the quiescent levels of the logic that drives the node. Both effects are presented together, in this paper, showing than both are a cause of errors in modern and future digital circuits. The paper groups both error mechanisms and shows how the global error rate is related with the voltage deviation and the period of the clock of the digital system.
引用
收藏
页码:152 / 155
页数:4
相关论文
共 50 条
  • [21] COMMUNICATION IN THE PRESENCE OF NOISE - PROBABILITY OF ERROR FOR 2 ENCODING SCHEMES
    RICE, SO
    [J]. BELL SYSTEM TECHNICAL JOURNAL, 1950, 29 (01): : 60 - 93
  • [22] ERROR-PROBABILITY OF 2DPSK WITH PHASE NOISE
    KAM, PY
    SEEK, KY
    TJHUNG, TT
    SINHA, P
    [J]. IEEE TRANSACTIONS ON COMMUNICATIONS, 1994, 42 (07) : 2366 - 2369
  • [23] PROBABILITY OF ERROR IN PAM SYSTEMS WITH INTERSYMBOL INTERFERENCE AND ADDITIVE NOISE
    JENQ, YC
    LIU, B
    THOMAS, JB
    [J]. IEEE TRANSACTIONS ON INFORMATION THEORY, 1977, 23 (05) : 575 - 582
  • [24] PROBABILITY OF ERROR IN CPSK SYSTEMS WITH INTERSYMBOL INTERFERENCE AND ADDITIVE NOISE
    JENQ, YC
    [J]. JOURNAL OF THE FRANKLIN INSTITUTE-ENGINEERING AND APPLIED MATHEMATICS, 1981, 311 (05): : 269 - 278
  • [26] A lower bound on the error probability for signals in white Gaussian noise
    Séguin, GE
    [J]. IEEE TRANSACTIONS ON INFORMATION THEORY, 1998, 44 (07) : 3168 - 3175
  • [27] Average Symbol Error Probability in the Presence of Network Interference and Noise
    Merola, Cristina
    Guidotti, Alessandro
    Di Renzo, Marco
    Santucci, Fortunato
    Corazza, Giovanni E.
    [J]. 2012 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS (ICC), 2012, : 2585 - 2590
  • [28] Error Masking With Approximate Logic Circuits Using Dynamic Probability Estimations
    Sanchez-Clemente, A.
    Entrena, L.
    Garcia-Valderas, M.
    [J]. PROCEEDINGS OF THE 2014 IEEE 20TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 2014, : 134 - 139
  • [29] Suppression of On-Chip Power Supply Noise Generated by a 64-Bit Static Logic ALU Block
    Charania, Tasreen
    Chuang, Pierce
    Opal, Ajoy
    Sachdev, Manoj
    [J]. 2012 IEEE/IFIP 20TH INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP (VLSI-SOC), 2012, : 201 - 206
  • [30] Probability based power aware error resilient coding
    Kim, M
    Oh, H
    Dutt, N
    Nicolau, A
    Venkatasubramanian, N
    [J]. 25TH IEEE INTERNATIONAL CONFERENCE ON DISTRIBUTED COMPUTING SYSTEMS WORKSHOPS, PROCEEDINGS, 2005, : 307 - 313