SoC: Simulation and damping of power supply noise

The analysis of full-chip IR and di/dt drop as well as package and on-chip resonance is very important for the system-on-chip design. Algorithms to optimize power distribution networks (PDNs) iteratively require fast methods to estimate the power supply noise. Additionally an efficient way to provide the complex input data for such a simulation is required. The simulation method used is based on a macromodel of the off-chip power supply and a 2D signal line model of the on-chip PDN. The on-chip PDN gets discretized in 2D signal line cells. We use admittance functions in each direction instead of resistances and inductances for these cells. Therefore, the frequency dependence due to the multiple return paths in different layers and further high frequency effects can be incorporated. One of the merits of this approach is that these admittance functions, which may vary all over the chip, can be efficiently calculated with a model order reduction algorithm directly from a Partial Element Equivalent Circuit (PEEC) model. The currents of the nonlinear devices are modeled as time varying current sources in parallel to capacitances and conductances. We use a fast transient simulation algorithm closely related to the Finite-Difference Time-Domain schemes to simulate the model. The method is well suited for iterative design improvements and irregular power grids. Combining the macromodel of the off-chip PDN with the reduced order model of the IC we investigate the effect of damping resistors and the possibility to optimize the power integrity, by increasing the damping resistors.