Capacitance Hysteresis in the High-k/Metal Gate-Stack From Pulsed Measurement

被引:11
|
作者
Duan, Tianli [1 ]
Ang, Diing Shenp [1 ]
机构
[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore
关键词
Capacitance transient; complementary-metal-oxide semicondutor (CMOS); rate-dependent hysteresis; sub-28-nm technology nodes; THRESHOLD VOLTAGE; C-V; TRAPS;
D O I
10.1109/TED.2013.2247764
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An unusual hysteresis is observed while measuring the capacitance-voltage (C-V) curve of the high-k/metal gate-stack using a pulsed-voltage technique. The hysteresis is found to vary only with the voltage ramp rate but not with the voltage pulse width. The C-V curve derived from the negative-to-positive (forward) voltage ramp has a consistently more positive flat band voltage than that obtained by the positive-to-negative (reverse) voltage ramp. The relative positions of the forward and reverse C - V curves are opposite to those measured using the quasi-static voltage-sweep method. Charge trapping/detrapping in the high-k oxide could not consistently account for these observations. An alternative explanation based on the lag in interface dipole response is proposed.
引用
收藏
页码:1349 / 1354
页数:6
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