Serial Concatenation of Reed Muller and LDPC Codes with Low Error Floor

被引:0
|
作者
Xiao, Xin [1 ]
Nasseri, Mona [2 ]
Vasic, Bane [1 ]
Lin, Shu [2 ]
机构
[1] Univ Arizona, Dept Elect & Comp Engn, Tucson, AZ 85721 USA
[2] Univ Calif Davis, Dept Elect & Comp Engn, Davis, CA 95616 USA
关键词
PARITY-CHECK CODES; POLAR CODES; PERFORMANCE; ALGORITHM; CAPACITY; GRAPHS;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we propose a concatenated coding scheme involving an outer Reed-Muller (RM) code and an inner Finite Field low-density parity check (LDPC) code of medium length and high rate. It lowers the error floor of inner Finite Field LDPC code. This concatenation scheme offers flexibility in design and it is easy to implement. In addition, the decoding works in a serial turbo manner and has no harmful trapping sets of size smaller than the minimum distance of the outer code. The simulation results indicate that the proposed serial concatenation can eliminate the dominant trapping sets of the inner Finite Field LDPC code.
引用
收藏
页码:688 / 693
页数:6
相关论文
共 50 条
  • [31] Concatenated Reed-Muller codes for unequal error protection
    Buch, G
    Burkert, F
    IEEE COMMUNICATIONS LETTERS, 1999, 3 (07) : 202 - 204
  • [32] Recursive error correction for general Reed-Muller codes
    Dumer, I
    Shabunov, K
    DISCRETE APPLIED MATHEMATICS, 2006, 154 (02) : 253 - 269
  • [33] Low-Floor Decoders for LDPC Codes
    Han, Yang
    Ryan, William E.
    IEEE TRANSACTIONS ON COMMUNICATIONS, 2009, 57 (06) : 1663 - 1673
  • [34] On the Construction of QC-LDPC Codes Based on Integer Sequence With Low Error Floor
    Tao, Xiongfei
    Chen, Xin
    Wang, Bifang
    IEEE COMMUNICATIONS LETTERS, 2022, 26 (10) : 2267 - 2271
  • [35] Code Construction Algorithm for Architecture Aware LDPC Codes with Low-Error-Floor
    Kania, Dariusz
    Sulek, Wojciech
    2008 IEEE REGION 8 INTERNATIONAL CONFERENCE ON COMPUTATIONAL TECHNOLOGIES IN ELECTRICAL AND ELECTRONICS ENGINEERING: SIBIRCON 2008, PROCEEDINGS, 2008, : 1 - 6
  • [36] Error robustness scheme for scalable video based on the concatenation of LDPC and turbo codes
    Ramzan, Naeem
    Wan, Shuai
    Izquierdo, Ebroul
    2007 IEEE INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, VOLS 1-7, 2007, : 3317 - 3320
  • [37] Serial concatenation of LDPC and space-time trellis codes with transmit antenna selection
    Aydin, Elif
    Altunbas, Ibrahim
    CIRCUITS AND SYSTEMS FOR SIGNAL PROCESSING , INFORMATION AND COMMUNICATION TECHNOLOGIES, AND POWER SOURCES AND SYSTEMS, VOL 1 AND 2, PROCEEDINGS, 2006, : 647 - 650
  • [38] Lowering the Error Floor of LDPC Codes Using Cyclic Liftings
    Asvadi, Reza
    Banihashemi, Amir H.
    Ahmadian-Attari, Mahmoud
    2010 IEEE INTERNATIONAL SYMPOSIUM ON INFORMATION THEORY, 2010, : 724 - 728
  • [39] Lowering the Error Floor of LDPC Codes Using Cyclic Liftings
    Asvadi, Reza
    Banihashemi, Amir H.
    Ahmadian-Attari, Mahmoud
    IEEE TRANSACTIONS ON INFORMATION THEORY, 2011, 57 (04) : 2213 - 2224
  • [40] Lowering the Error Floor of ADMM Penalized Decoder for LDPC Codes
    Jiao Xiaopeng
    Mu Jianjun
    CHINA COMMUNICATIONS, 2016, 13 (08) : 127 - 135