True Random Number Generation from Bang-Bang ADPLL Jitter

In this work a concept for true random number generator from jitter in bang-bang ADPLLs within systems-on-chip is presented. For this purpose the phase-frequency detector (PFD) output of an existing ADPLL clock generator bit is directly used as entropy source with zero power and chip area overhead. The randomness properties of the PFD data stream are analyzed and a lightweight, fully synthesizable entropy extractor circuit is proposed. The circuit is prototyped in 28nm CMOS technology based on an ADPLL circuit with 100MHz reference clock frequency. The true random number generator achieves a 12.5 MBit/s random data stream which passes the dieharder test-suite at only 1.55 pJ/Bit. The post-processor has an area overhead of only 169 mu m(2) in addition to the ADPLL clock generator.