Leakage Reduction by Test Pattern Reordering

被引:1
|
作者
Chakraborty, Shrabanti [1 ]
Sarkar, Trupa [1 ]
Pradhan, Sambhu Nath [1 ]
机构
[1] Natl Inst Technol, Dept ECE, Agartala, India
关键词
D O I
10.1007/978-981-10-2999-8_5
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:55 / 68
页数:14
相关论文
共 50 条
  • [1] An Improved Test Pattern Reordering Framework Targeting Test Power Reduction
    Maity, Hillol
    Chattopadhyay, Santanu
    Sengupta, Indranil
    Bhattacharya, Parthajit
    Patankar, Girish
    2021 IEEE INTERNATIONAL TEST CONFERENCE INDIA (ITC INDIA), 2021, : 73 - 78
  • [2] Input vector reordering for leakage power reduction in FPGAs
    Hassan, Hassan
    Anis, Mohab
    Elmasry, Mohamed
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2008, 27 (09) : 1555 - 1564
  • [3] Transistor and pin reordering for leakage reduction in CMOS circuits
    Chun, Jae Woong
    Chen, C. Y. Roger
    MICROELECTRONICS JOURNAL, 2016, 53 : 25 - 34
  • [4] Leakage power reduction using the body bias and pin reordering technique
    Chun, Jae Woong
    Chen, Chien-Yi Roger
    IEICE ELECTRONICS EXPRESS, 2016, 13 (03):
  • [5] Scan architecture modification with test vector reordering for test power reduction
    Giri, Chandan
    Choudhary, Pradeep Kumar
    Chattopadhyay, Santanu
    2007 INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS, VOLS 1 AND 2, 2007, : 449 - 452
  • [6] Critical-Area-Aware Test Pattern Generation and Reordering
    Inuyama, Shingo
    Iwasaki, Kazuhiko
    Arai, Masayuki
    2016 IEEE 25TH ASIAN TEST SYMPOSIUM (ATS), 2016, : 191 - 196
  • [7] Reordering-Based Test Pattern Reduction Considering Critical Area-Aware Weighted Fault Coverage
    Arai, Masayuki
    Iwasaki, Kazuhiko
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2017, E100A (07) : 1488 - 1495
  • [8] Reordering and Test Pattern Generation for Reducing Launch and Capture Power
    Stanis, Jonisha S.
    Antony, Maria S.
    2015 INTERNATIONAL CONFERENCE ON INNOVATIONS IN INFORMATION, EMBEDDED AND COMMUNICATION SYSTEMS (ICIIECS), 2015,
  • [9] Transistor and pin reordering for gate oxide leakage reduction in dual Tox circuits
    Sultania, AK
    Sylvester, D
    Sapatnekar, SS
    IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS, 2004, : 228 - 233
  • [10] DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-In
    Kao, Wei-Chung
    Chuang, Wei-Shun
    Lin, Hsiu-Ting
    Li, James Chien-Mo
    Manquinho, Vasco
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2010, 18 (03) : 392 - 400