Analyzing fault models for reversible logic circuits

被引：0

作者：

Zhong, Jing ^{[1
]}

Muzio, Jon C. ^{[1
]}

机构：

[1] Univ Victoria, Victoria, BC V8W 3P6, Canada

来源：

2006 IEEE CONGRESS ON EVOLUTIONARY COMPUTATION, VOLS 1-6 | 2006年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Reversible logic computing is a rapidly developing research area. Testing such circuits is obviously an important issue. In this paper, we consider a new fault model, labeled crosspoint faults, for reversible logic circuits. A randomized Automatic Test Pattern Generation algorithm targeting this specific kind of fault is introduced and analyzed. Simulation results show that the algorithm yields very good performance. The relationship between the crosspoint faults and stuck-at faults is also investigated. We show that the crosspoint fault model is a better fault model for reversible circuits since it dominates the traditional stuck-at fault model in most instances.

引用

页码：2407 / 2412

页数：6

共 50 条

[21] Improved Fault Diagnosis for Reversible Circuits
Zhang, Hongyan
Wille, Robert
Drechsler, Rolf
2011 20TH ASIAN TEST SYMPOSIUM (ATS), 2011, : 207 - 212
[22] Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates
Parvin, Sajjad
Altun, Mustafa
IEEE ACCESS, 2019, 7 : 163939 - 163947
[23] Energy recovery circuits using reversible and partially reversible logic
Ye, YB
Roy, K
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 1996, 43 (09): : 769 - 778
[24] FAULT MASKING IN COMBINATIONAL LOGIC CIRCUITS
DIAS, FJO
IEEE TRANSACTIONS ON COMPUTERS, 1975, C 24 (05) : 476 - 482
[25] Reversible fault-tolerant logic
Boykin, PO
Roychowdhury, VP
2005 INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS AND NETWORKS, PROCEEDINGS, 2005, : 444 - 453
[26] Online Fault Detection in Reversible Logic
Nayeem, N. M.
Rice, J. E.
2011 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT), 2011, : 426 - 434
[27] A Survey on Adiabatic Logic Families for Implementing Reversible Logic Circuits
Bommi, R. M.
Raja, Selvakumar S.
2018 IEEE INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND COMPUTING RESEARCH (IEEE ICCIC 2018), 2018, : 45 - 48
[28] Reversible fault-tolerant logic
Boykin, P.O. (boykin@ece.ufl.edu), IEEE Comput. Soc. Tech. Commit. on Fault-Tolerant Comput.; IFIP WG 10.4 on Dependable Comput. and Fault Tolerance; IEICE Tech. Group on Dependable Comput. (Institute of Electrical and Electronics Engineers Computer Society):
[29] A Classical Propositional Logic for Reasoning About Reversible Logic Circuits
Axelsen, Holger Bock
Gluck, Robert
Kaarsgaard, Robin
LOGIC, LANGUAGE, INFORMATION, AND COMPUTATION, 2016, 9803 : 52 - 67
[30] A Review on Fundamentals of Ternary Reversible Logic Circuits
Rani, P. Mercy Nesa
Thangkhiew, Phrangboklang Lyngton
2020 INTERNATIONAL CONFERENCE ON COMPUTATIONAL PERFORMANCE EVALUATION (COMPE-2020), 2020, : 738 - 743

← 1 2 3 4 5 →