A Hardware Implementation of SOM Neural Network Algorithm

被引：1
|
作者：
Yi, Qian [1 ]
机构：
[1] Taishan Univ, Dept Informat Sci & Technol, Tai An, Shandong, Peoples R China
来源：
2018 INTERNATIONAL CONFERENCE ON SENSOR NETWORKS AND SIGNAL PROCESSING (SNSP 2018) | 2018年
关键词：
SOM; FPGA; architecture; parallel;
D O I：
10.1109/SNSP.2018.00101
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Aiming at the real-time problem of SOM(Self-Organizing Feature Map) neural network algorithm based on FPGA(Field Programmable Gate Array), this paper analyzes the parallelism and resource reuse of algorithm process, presents a parallel architecture to implement the algorithm, and gives the hardware design method of the key modules in the architecture. It is simulated by Modelsim and runs on the FPGA development board. The experimental results show that the architecture can ensure the performance of neural network and the circuit has a high processing speed.
引用
收藏
页码：508 / 511
页数：4
相关论文
共 50 条
  • [41] Hardware implementation of neural network with. expansiuble and reconfigurable architecture
    Yun, SB
    Kim, YJ
    Dong, SS
    Lee, CH
    [J]. ICONIP'02: PROCEEDINGS OF THE 9TH INTERNATIONAL CONFERENCE ON NEURAL INFORMATION PROCESSING: COMPUTATIONAL INTELLIGENCE FOR THE E-AGE, 2002, : 970 - 975
  • [42] Hardware implementation of a mixed analog-digital neural network
    Izak, R
    Trott, K
    Zahn, T
    Markl, U
    [J]. COMPUTATIONAL INTELLIGENCE: THEORY AND APPLICATIONS, 1997, 1226 : 560 - 560
  • [43] Advancements in Perceptron Hardware for Efficient Implementation in Artificial Neural Network
    Mohaidat, Tamador
    Khalil, Kasem
    [J]. 2024 IEEE 3RD INTERNATIONAL CONFERENCE ON COMPUTING AND MACHINE INTELLIGENCE, ICMI 2024, 2024,
  • [44] Hardware Implementation of Convolutional Neural Network for Face Feature Extraction
    Ding, Ru
    Tian, Xuemei
    Bai, Guoqiang
    Su, Guangda
    Wu, Xingjun
    [J]. 2019 IEEE 13TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2019,
  • [45] Hardware implementation of CMAC neural network with reduced storage requirement
    Coll of Technology and Commerce, Kaohsiung, Taiwan
    [J]. IEEE Trans Neural Networks, 6 (1545-1556):
  • [46] Exploiting Weight Statistics for Compressed Neural Network Implementation on Hardware
    Kashikar, Prachi
    Sinha, Sharad
    Verma, Ajeet Kumar
    [J]. 2021 IEEE 3RD INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE CIRCUITS AND SYSTEMS (AICAS), 2021,
  • [47] Hardware implementation of CMAC neural network with reduced storage requirement
    Ker, JS
    Kuo, YH
    Wen, RC
    Liu, BD
    [J]. IEEE TRANSACTIONS ON NEURAL NETWORKS, 1997, 8 (06): : 1545 - 1556
  • [48] Hardware implementation of CMAC neural network using FPGA approach
    Chung, Chao-Ming
    Lin, Chih-Min
    Chiang, Ching-Tsan
    Yeung, Daniel S.
    [J]. PROCEEDINGS OF 2007 INTERNATIONAL CONFERENCE ON MACHINE LEARNING AND CYBERNETICS, VOLS 1-7, 2007, : 2005 - +
  • [49] Digital hardware implementation of a radial basis function neural network
    Nguyen Phan Thanh
    Kung, Ying-Shieh
    Chen, Seng-Chi
    Chou, Hsin-Hung
    [J]. COMPUTERS & ELECTRICAL ENGINEERING, 2016, 53 : 106 - 121
  • [50] Hardware implementation of a combined radial basis function neural network
    Liang, Yan
    Jin, Dongming
    [J]. Qinghua Daxue Xuebao/Journal of Tsinghua University, 2009, 49 (10): : 1692 - 1695
12345