Electromagnetic and Thermal Co-Analysis for distributed co-design and co-simulation of chip, package and board

被引:0
|
作者
Wane, Sidina [1 ]
Kuo, An-Yu
机构
[1] NXP Semicond, Campus Effisci, F-14000 Caen, France
关键词
chip-package-board co-design/co-simulation; Electromagnetic and Thermal Co-Analysis;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper discusses Electromagnetic (En and Thermal Co-Analysis for chip, package and board co-design and co-simulation. The limitation of classical divide-and-conquer approaches based on cascading techniques are investigated in reference to global methodologies where Chip, Package and Board am simulated using one single model methodology. Cascade and single model methodologies are applied to a real-world NXP-Semiconductors System-in-Package carrier product for simultaneous co-design and co-simulation of Chip, Package and Board, the obtained results are compared both for Full-wave and Quasi-static assumptions. A global use-model combining EM simulation with thermal analysis is proposed towards multi-physics oriented co-design and co-simulation.
引用
收藏
页码:423 / +
页数:2
相关论文
共 50 条
  • [21] Co-simulation platforms for co-design of networked control systems: An overview
    Li, Weilin
    Zhang, Xiaobin
    Li, Huimin
    CONTROL ENGINEERING PRACTICE, 2014, 23 : 44 - 56
  • [22] Chip and package co-design technique for clock networks
    Zhu, Q
    Dai, WWM
    1996 IEEE MULTI-CHIP MODULE CONFERENCE, PROCEEDINGS, 1996, : 160 - 163
  • [23] Interaction of co-design and co-simulation, based on multi-block-systems
    Siemers, C
    Möller, DPF
    SIMULATION IN INDUSTRY'99: 11TH EUROPEAN SIMULATION SYMPOSIUM 1999, 1999, : 36 - 40
  • [24] Electromagnetic and Thermal Co-Analysis of an Implanted Dipole Antenna
    Alemaryeen, Ala
    Noghanian, Sima
    IEEE OPEN JOURNAL OF ANTENNAS AND PROPAGATION, 2024, 5 (06): : 1539 - 1550
  • [25] Chip-Package-PCB Co-Simulation for Power Integrity Design at the Early Design Stage
    Uematsu, Yutaka
    Taniguchi, Hitoshi
    Toyama, Masahiro
    Yagyu, Masayoshi
    Osaka, Hideki
    2015 IEEE 4TH ASIA-PACIFIC CONFERENCE ON ANTENNAS AND PROPAGATION (APCAP), 2015, : 451 - 452
  • [26] Chip/Package/Board Co-Design Methodology Applied to Full-Custom Heterogeneous Integration
    Brandtner, Thomas
    Pressel, Klaus
    Floman, Natalia
    Schultz, Michael
    Vogl, Michael
    2020 IEEE 70TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2020), 2020, : 1718 - 1727
  • [27] Effects of Critically Damped Total PDN Impedance in Chip-Package-Board Co-Design
    Kobayashi, Ryota
    Kubo, Genki
    Otsuka, Hiroki
    Mido, Tatsuya
    Kobayashi, Yoshinori
    Fujii, Hideyuki
    Sudo, Toshio
    2012 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC), 2012, : 538 - 543
  • [28] Chip-package co-design of a 4.7 GHz VCO
    Donnay, S
    Vaesen, K
    Pieters, P
    Diels, W
    Wambacq, P
    de Raedt, W
    Beyne, E
    Engels, M
    ICM'99: ELEVENTH INTERNATIONAL CONFERENCE ON MICROELECTRONICS - PROCEEDINGS, 1999, : 145 - 148
  • [29] Chip-package co-design of a 4.7 GHz VCO
    Vaesen, K
    Donnay, S
    Pieters, P
    Carchon, G
    Diels, W
    Wambacq, P
    De Raedt, W
    Beyne, E
    Engels, M
    Bolsens, I
    2000 HD INTERNATIONAL CONFERENCE ON HIGH-DENSITY INTERCONNECT AND SYSTEMS PACKAGING, 2000, 4217 : 301 - 306
  • [30] System Aware Floorplanning for Chip-Package Co-design
    Pan, Tse-Han
    Franzon, Paul D.
    Srinivas, Vaishnav
    Nagarajan, Mahalingam
    Popovic, Darko
    2023 IEEE 32ND CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, EPEPS, 2023,