Built-in self-test for flash memory embedded in SoC

被引:0
|
作者
Banerjee, S [1 ]
Chowdhury, DR [1 ]
机构
[1] Indian Inst Technol, Dept Comp Sci & Engn, Kharagpur 721302, W Bengal, India
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Flash memories are a type of non-volatile memory, which are becoming more and more popularfor System-on-Chip. But, flash memories are suffered by different types of disturb faults. In the present paper, some new disturb faults that may appear in flash memory are proposed. A modifies March algorithm is developed to detect these faults. Finally, an embedded processor-based Built-In Self-Test (BIST) design is implemented for embedded memories. The proposed method utilizes the concept of reusing the processor in SoC environment. By reusing the embedded processor, the area overhead due to BIST can be reduced to a great extent. The area overhead is only due to the circuits required to design memory wrapper cell. The experimental results show that the area overhead due to BIST is less than 1% for a typical 256K flash memory.
引用
收藏
页码:379 / +
页数:2
相关论文
共 50 条
  • [21] On Built-In Self-Test for Adders
    Pulukuri, Mary D.
    Stroud, Charles E.
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2009, 25 (06): : 343 - 346
  • [22] BUILT-IN SELF-TEST STRUCTURES
    MCCLUSKEY, EJ
    IEEE DESIGN & TEST OF COMPUTERS, 1985, 2 (02): : 29 - 36
  • [23] Economics of built-in self-test
    Ungar, LY
    Ambler, T
    IEEE DESIGN & TEST OF COMPUTERS, 2001, 18 (05): : 70 - 79
  • [24] On Built-In Self-Test for Multipliers
    Pulukuri, Mary D.
    Starr, George J.
    Stroud, Charles E.
    IEEE SOUTHEASTCON 2010: ENERGIZING OUR FUTURE, 2010, : 25 - 28
  • [25] On Built-In Self-Test for Adders
    Mary D. Pulukuri
    Charles E. Stroud
    Journal of Electronic Testing, 2009, 25 : 343 - 346
  • [26] A built-in self-test and self-diagnosis scheme for embedded SRAM
    Wang, CW
    Wu, CF
    Li, JF
    Wu, CW
    Teng, T
    Chiu, K
    Lin, HP
    PROCEEDINGS OF THE NINTH ASIAN TEST SYMPOSIUM (ATS 2000), 2000, : 45 - 50
  • [27] BUILT-IN SELF-TEST TECHNIQUES
    MCCLUSKEY, EJ
    IEEE DESIGN & TEST OF COMPUTERS, 1985, 2 (02): : 21 - 28
  • [28] A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM
    Chih-Wea Wang
    Chi-Feng Wu
    Jin-Fu Li
    Cheng-Wen Wu
    Tony Teng
    Kevin Chiu
    Hsiao-Ping Lin
    Journal of Electronic Testing, 2002, 18 : 637 - 647
  • [29] Built-in self-test and repair (BISTR) techniques for embedded RAMS
    Lu, SK
    Huang, SC
    RECORDS OF THE 2004 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING, 2004, : 60 - 64
  • [30] Built-in self-test for analog-to-digital converters in SoC applications
    Wibbenmeyer, J
    Chen, CIH
    IECON 2005: THIRTY-FIRST ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY, VOLS 1-3, 2005, : 2231 - 2236