A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion

This paper proposes a synthesizable digital LDO that is implemented with standard-cell-based digital design flow. With inverter chains as voltage-controlled delay lines, the difference between output and reference voltages is converted into delay difference, then compared in time-domain. Since the time-domain difference is straightforwardly captured by a phase detector that consists of a D-FF, the proposed LDO does not need an analog voltage comparator, which requires careful manual design. The prototype of the proposed LDO is fabricated in 65nm standard CMOS technology with 0.015 mm(2) area occupation. The measurement results show that with 10.4 MHz internal clock the tracking response to 200mV switching of the reference voltage is similar to 4.5 mu s and the transient response to 5mA change of the load current is similar to 6.6 mu s. The quiescent current consumed by the LDO core is as low as 35.2 mu A at 10mA load current, which leads to 99.6% current efficiency.