A high-performance low-power 2-D 8 x 8 IDCT processor with asynchronous pipeline

被引：0

作者：

Xu, M ^{[1
]}

Jian, G ^{[1
]}

Jie, C ^{[1
]}

机构：

[1] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China

来源：

2005 6TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, BOOKS 1 AND 2 | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a high-performance low-power 2-D IDCT processor for video applications. Based on multiply-accumulator architecture, the processor can meet the high-speed requirement of HDTV. To save power consumption, the processor employs asynchronous pipeline in which local clocks are enabled only when there is an operation to perform. Compared with conventional synchronous pipelined design, the proposed design exhibits an average power saving of 40%.

引用

页码：290 / 293

页数：4

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