Chip Package Interaction in Micro Bump and TSV Structure

The purpose of this paper is chip package interaction(CPI) of fine pitch micro bump and trough silicon via(TSV). We focus on hot temperature storage(HTS) and electromigration (EM) due to its strong impact on reliability. In chip on chip (CoC) structure, Cu and Ni was used to evaluate under bump metallurgy(UBM) reliability. TSV stacked chip with Cu UBM was evaluated as well. There is no resistance degradation at CoC flip-chip structure (no TSV structure), but resistance of TSV stacked chip was increased after 1000 hours at HTS 150 degrees C. The cause of resistance increase is intermetallic(IMC) penetration into TSV during annealing process. It strongly recommends that effective barrier metal is required to slow down IMC formation. In addition, EM test was performed to investigate resistance against current stress for small size micro bump at various current densities and temperatures. Ni UBM and Cu UBM show good EM resistance even its small size. Cu UBM shows better EM life time than that of Ni UBM due to less Joule heat generation during EM test. However, EM with TSV structure shows less lifetime due to Cu metal line damage. Finally, we demonstrate preliminary look-ahead qualification such as HTS, Preconditioning, temperature humidity bias(THB), and temperature cycle(TC) for our TSV stacked product.