DARK-Adders: Digital Hardware Trojan Attack on Block-based Approximate Adders

被引:2
|
作者
Mishra, Vishesh [1 ]
Hassan, Neelofar [1 ]
Mehta, Akshay [2 ]
Chatterjee, Urbi [1 ]
机构
[1] Indian Inst Technol, Dept Comp Sci & Engn, Kanpur, Uttar Pradesh, India
[2] Indian Inst Technol, Dept Elect Engn, Kanpur, Uttar Pradesh, India
关键词
Approximate Computing; Hardware Security; Trojan attacks;
D O I
10.1109/VLSID57277.2023.00080
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In recent times, approximate computing techniques have emerged as a popular computing paradigm that can significantly minimize consumption of resources at the cost of bounded loss in accuracy of results. More specifically, approximate arithmetic circuits such as addition and multiplication architecture have been widely deployed to benefit image processing, machine learning and other error-resilient applications. However, a major drawback attributed with approximate architectures is that the results generated by them are probabilistic in nature. This indeterminism in input-output characteristics results in security breaches during post-silicon validation. In other words, the relaxation in precision may lower the standard of testing metrics, thus making block-based approximate designs vulnerable to security attacks. This work proposes a digital Hardware Trojan Horse (HTH) that renders approximate adder circuits inefficient. The proposed attack exploits the probabilistic nature of approximate designs to successfully implant the HTH. The presented HTH replaces the original sum-bit generation logic in a 1-bit full adder widely present as a building block in a major class of block-based low latency approximate adders. Experimental results showcase that insertion of HTH in state-of-the-art approximate adders can reduce the end applications accuracy by 2-13%, and 24-31% when Trojan is inserted at Least significant Bit side (LSBs) and Most Significant Bit (MSBs) respectively. Our proposed Trojan does not add significant area overhead upon successful insertion. Additionally, the obtained results also signify that block-based low latency approximate adders with N number of blocks are N/2 times more vulnerable to security attacks than their binary segmentation counterparts. Experimental results also demonstrate that the impact of a digital HTH may be considered to be relatively mild in exact computing designs, it proves to alter the intended behaviour of approximate circuits when tested across real time applications such as machine learning and image processing.
引用
收藏
页码:371 / 376
页数:6
相关论文
共 50 条
  • [1] Design and Analysis of High Performance Heterogeneous Block-based Approximate Adders
    Farahmand, Ebrahim
    Mahani, Ali
    Hanif, Muhammad Abdullah
    Shafique, Muhammad
    [J]. ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2023, 22 (06)
  • [2] An Efficient Method for Calculating the Error Statistics of Block-Based Approximate Adders
    Wu, Yi
    Li, You
    Ge, Xiangxuan
    Gao, Yuan
    Qian, Weikang
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 2019, 68 (01) : 21 - 38
  • [3] Comparison of Hardware Accelerator of Matrix Multiplication with Approximate Adders
    Chung, Yunchul
    Cho, Manhee
    Kim, Youngmin
    [J]. 2021 INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION, AND COMMUNICATION (ICEIC), 2021,
  • [4] Security Implications of Approximation: A Study of Trojan Attacks on Approximate Adders and Multipliers
    Mishra, Vishesh
    Mittal, Sparsh
    Mishra, Nirbhay
    Singhal, Rekha
    [J]. PROCEEDINGS OF THE 37TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, VLSID 2024 AND 23RD INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, ES 2024, 2024, : 511 - 516
  • [5] Detecting Hardware Faults in Approximate Adders via Minimum Redundancy
    Tsounis, Ioannis
    Agiakatsikas, Dimitris
    Psarakis, Mihalis
    [J]. 2023 IEEE 29TH INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN, IOLTS, 2023,
  • [6] A Power-Efficient FFT Hardware Architecture Exploiting Approximate Adders
    Ferreira, Guilherme
    Pereira, Pedro T. L.
    Paim, Guilherme
    Costa, Eduardo
    Bampi, Sergio
    [J]. 2021 IEEE 12TH LATIN AMERICA SYMPOSIUM ON CIRCUITS AND SYSTEM (LASCAS), 2021,
  • [7] Accuracy enhancement of equal segment based approximate adders
    Dutt, Sunil
    Nandi, Sukumar
    Trivedi, Gaurav
    [J]. IET COMPUTERS AND DIGITAL TECHNIQUES, 2018, 12 (05): : 206 - 215
  • [8] Exploring Approximate Adders for Power-Efficient Harmonics Elimination Hardware Architectures
    Pereira, Pedro T. L.
    Paim, Guilherme
    Ferreira, Guilherme
    Costa, Eduardo
    Almeida, Sergio
    Bampi, Sergio
    [J]. 2021 IEEE 12TH LATIN AMERICA SYMPOSIUM ON CIRCUITS AND SYSTEM (LASCAS), 2021,
  • [9] Low-Power Digital Signal Processing Using Approximate Adders
    Gupta, Vaibhav
    Mohapatra, Debabrata
    Raghunathan, Anand
    Roy, Kaushik
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2013, 32 (01) : 124 - 137
  • [10] Analysis, Modeling and Optimization of Equal Segment Based Approximate Adders
    Dutt, Sunil
    Dash, Satyabrata
    Nandi, Sukumar
    Trivedi, Gaurav
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 2019, 68 (03) : 314 - 330