Analysis, Modeling and Optimization of Equal Segment Based Approximate Adders

Over the past decade, several approximate adders have been proposed in the literature based on the design concept of Equal Segment Adder (ESA). In this approach, an N-bit adder is segmented into several smaller and independent equally sized accurate sub-adders. An N-bit ESA has two primary design parameters: (i) Segment size (k), which represents the maximum length of carry propagation; and (ii) Overlapping bits (l), which represents the minimum number of bits used in carry prediction, where 1 <= k < N and 0 <= l < k. Based on the combinations of k and l, an N-bit ESA has N(N - 1)/2 possible configurations. In this paper, we analyse ESAs and propose analytical models to estimate accuracy, delay, power and area of ESAs. The key features of the proposed analytical models are that: (i) They are generalized, i.e., work for all possible configurations of an N-bit ESA; and (ii) They are superior (i.e., estimate more accurately) or at par to the existing analytical models. From the proposed analytical models, we observe that in an N-bit ESA, there exist multiple (more than one) configurations which exhibit similar accuracy. However, these configurations exhibit different delay, power and area. Therefore, for a given accuracy, the configurations which provide minimal delay, power and/or area need to be known apriori for efficient, intelligent and goal oriented implementations of ESAs. In this regard, we present an optimization framework that exploits the proposed analytical models to find the optimal configurations of an N-bit ESA. Further, we know that accuracy of an ESA does not depend on the adder architecture used to implement it, however, its delay, power and area depend significantly. Consequently, the optimal configurations vary with adder architectures used to implement the ESA. In order to cover a wide range of adders, we consider three types of adder architecture in our analysis: (i) Architectures having smaller area (O(N)); (ii) Architectures having smaller delay (O(log(2)N)); and (iii) Architectures having in-between delay (O(N/4)) and area (O(2N)).