Investigation of Single Event Transient Induced by Process Variability in 14 nm High-k/Metal Gate SOI FinFET Devices

With the down scaling of device dimensions, FinFET structure faces the problem of the increasing process variability which results to the device performance mismatch. By technology computer-aided design (TCAD) numerical simulation, a high-k/metal gate silicon-on-insulator (SOI) FinFET at 14 nm technology node is presented, which is calibrated by the experiment data. The influences of the work function and the oxide thickness variation on single event transient (SET) characteristic are systematically studied and analyzed. The statistical analysis of the effects of three profile oxide thickness mismatch and variation on SET is also performed. The results show that as the equivalent oxide thickness varies from 0.41 nm to 0.61 nm, SET current peak increases from 377.92 mu A to 392.08 mu A and the collected charge increases from 1.265fC to 1.271fC due to the increased threshold voltage, respectively. Due to the combination electron concentration and recombination rate, when the work function varies from 4.36 eV to 4.6 eV, the transient current peak decreases from 387.23 mu A to 363.61 mu A and the collected charge reduces from 1.269fC to 1.258fC, respectively. Compared with the profile with shorter gate width, the effect of the oxide thickness variation with the longer gate width on SET is more significant. The standard deviation and normalized deviation of SET current peak and collected charge are 7.35 mu A and 0.03fC, 1.89% and 2.57%, respectively.