A Digital Jitter Compensation Technique for Analog-to-Digital Converters

For an ADC that periodically converts a time-varying analog input, the jitter in the ADC's sampling clock introduces sampling errors, degrading the ADC's dynamic performance. This paper describes a jitter compensation technique to mitigate the effect of sampling clock jitters. Clock jitter is detected by using an extra ADC that samples a reference clock. Sampling errors are then canceled by using a digital differentiator with the acquired jitter estimates. Experiment on a test chip shows that this technique improves the SNR performance of a 12-bit 247-MS/s ADC from 51.9 dB to 56.3 dB when the input is an 80-MHz 1-dBFS sinewave. A sampling clock with 4.89 ps rms jitter drives the ADC.