A statistical background calibration technique for flash analog-to-digital converters

被引：0

作者：

Huang, CC ^{[1
]}

Wu, JT ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan

来源：

2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new background calibration technique is described to digitally trim the input-referred offset voltage of comparators in a high-speed flash analog-to-digital converters. The polarity of comparator's offset is detected by observing the output code density of a random chopping comparator. Binary feedback is used to adjust the comparator's offset. All calibration processing is performed in the digital domain. thus minimizing the overhead for analog circuitry. Two key design parameters are the comparator's trimming step and the thresholds of a peak detector, which determine the offset's standard deviation and the time constant of the calibration loop.

引用

页码：125 / 128

页数：4

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