Electrically Doped PNPN Tunnel Field-Effect Transistor Using Dual-Material Polarity Gate with Improved DC and Analog/RF Performance

A new structure for PNPN tunnel field-effect transistors (TFETs) has been designed and simulated in this work. The proposed structure incorporates the polarity bias concept and the gate work function engineering to improve the DC and analog/RF figures of merit. The proposed device consists of a control gate (CG) and a polarity gate (PG), where the PG uses a dual-material gate (DMG) structure and is biased at -0.7 V to induce a P+ region in the source. The PNPN structure introduces a local minimum on the conduction band edge curve at the tunneling junction, which dramatically reduces the tunneling width. Furthermore, we show that incorporating the DMG architecture further enhances the drive current and improves the subthreshold slope (SS) characteristics by introducing an additional electric field peak. The numerical simulation reveals that the electrically doped PNPN TFET using DMG improves the DC and analog/RF performances in comparison to a conventional single-material gate (SMG) device.