Engineering negative differential resistance in negative capacitance Quad-FinFET

In this work, a systematically analysis of the Negative Capacitance (NC) Quad-FinFET structure is carried out where we determine the optimal FE layer thickness that enables hysteresis-free transfer characteristics. However, negative differential resistance (NDR) is introduced along with the increased FE-layer thickness, which is not desirable for application in analog circuits. Through the implementation of an asymmetric drain length extension and a high-k Si3N4 spacer, negative differential resistance (NDR) can be mitigated. In addition, the relatively poor analog performance generally seen in conventional FinFET structures are overcome in the drain engineered NC Quad-FinFET structure with gate spacer resulting in significant improvement in performance parameters such as transconductance, output conductance and intrinsic gain. The integration of NC Quad-FinFET as a digital inverter is carried out where the circuit propagation delay is decreased by 27.65% with drain length extension and inclusion of Si3N4 spacer. Thus, through these device optimization techniques, the NC Quad-FinFET structure shows significant improvement in both analog and digital device performance parameters.