Cryogenic Characterization of 40nm CMOS for Quantum Control Applications

CMOS circuits operating at cryogenic temperatures are gaining momentum as a promising approach for scaling up future quantum processors. However, standard SPICE models provided by the foundries do not accurately capture device behavior in cryogenic environments, thus hindering circuit design and optimization. Rigorous cryogenic characterization of CMOS devicesis required to capture their performance shift at very low temperatures. This work reports our 40nm CMOS transistor test chip and its preliminary characterization at 8 K. This serves as an important step towards developing efficient cyrogenic CMOS chip for quantum control applications.