Adaptive neural acceleration unit based on heterogeneous multicore hardware architecture FPGA and software-defined hardware

This study is anchored in a heterogeneous multicore hardware architecture, specifically Field Programmable Gate Arrays (FPGAs), and software-defined hardware. It employs dynamic planning for the reconfiguration of a software-defined System-on-Chip (SOC) to expedite neural network processes. The reconfigured software-defined SOC serves as an efficient data processor, facilitating the hybrid development and verification of domain-specific System-on-Chip architectures, adhering to the Advanced Microcontroller Bus Architecture (AMBA) standard. The proposed block data trimming methodology significantly enhances overall hybrid computing efficiency by mitigating throughput limitations inherent in Systolic array hardware. The designed Systolic array Matrix Multiply Unit (MMU) is evaluated for a maximum MMU size of 32 x 32 and 1,024 Multiply Accumulator (MAC) units. Hybrid dynamic circuits are devised for the synthesis of int8, int16, int32, and int64 data types and associated logic circuits to validate the performance of parallel computing. It is anticipated that this proposed system can find utility in the development and deployment of unmanned devices, as well as in the integration of deep learning and multi-sensory fusion involving acoustic, tactile, and force sensory components.