High-Speed and Low-Power Embedded TEC BCH Scheme for ReRAM Array

被引：0

作者：

Zhang, Kun ^{[1
,2
,3
]}

Liu, Haiyang ^{[4
]}

Zheng, Xu ^{[1
,2
,3
]}

Xu, Xiaoxin ^{[1
,2
]}

Hu, Hongyang ^{[1
,2
,3
]}

Zhang, Junyu ^{[1
,2
]}

机构：

[1] Chinese Acad Sci, Inst Microelect, State Key Lab Fabricat Technol Integrated Circuits, Beijing 100029, Peoples R China

[2] Chinese Acad Sci, Inst Microelect, Lab Microelect Devices & Integrated Technol, Beijing 100029, Peoples R China

[3] Univ Chinese Acad Sci, Beijing 100049, Peoples R China

[4] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2023年 / 20卷 / 15期

基金：

中国国家自然科学基金;

关键词：

TEC BCH; ReRAM; fully-parallel decoder; adaptive error correction; composite field; DESIGN;

D O I：

10.1587/elex.20.20230193

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes an embedded TEC BCH scheme for ReRAM array, which is capable of low access time and uniform error distribution. The high speed decoder with SBSA is proposed with a fully-parallel architecture. An optimized adaptive error correction approach is utilized to reduce the power consumption. Furthermore, the composite field arithmetic is used to minimize the logical size. For the performance evaluation, the decoder is implemented on a Xilinx Virtex-7 FPGA, and synthesized with 65nm CMOS technology, which can achieve a 62.72 Gb/s throughput at a decoding frequency of 490MHz and 0.95ns decoding delay with a 774.1 mu W power consumption.

引用

页数：6

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