Risk Assessment of Hybrid Low Temperature Solder on Surface Mount Technology and Board Level Reliability for BGA Packages

被引:2
|
作者
Lee, Jihyun [1 ]
Park, Yongsung [1 ]
Lee, Junho [1 ]
Lee, Kangjoon [1 ]
Ryu, Hansung [1 ]
Jung, JeeHyun [1 ]
Kim, Kilsoo [1 ]
机构
[1] Samsung Elect Co Ltd, Hwaseong Si, Gyeonggi Do, South Korea
关键词
BGA solder joints; low temperature solder paste; SMT; BLR;
D O I
10.1109/ECTC51909.2023.00115
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Low temperature solder (LTS) enables surface mount technology (SMT) at a lower reflow temperature than the traditional Sn-Ag-Cu (SAC) alloy. This allows lower energy cost and CO2 emission during assembly, and its mass production adoption is spreading to various applications. In this study, SMT and board level reliability (BLR) risks of LTS hybrid solder joint system, where package with SAC solder balls are joined with LTS paste are evaluated. Results show that LTS hybrid system is very sensitive to reflow profile. When the reflow peak temperature is not high enough, some solders did not fully collapsed, which increased the Head-in-Pillow (HiP) risk and also showed early PCB side solder cracks during thermal cycling (TC). Higher peak reflow temperature resulted in more stable solder joint shape; however, Bi element with brittle characteristics spreading to package side actually decreased the TC performance. Amount of Bi Mixed Ratio (BMR), which is related to reflow temperature, seems to explain the TC performance and finite element analysis (FEA) also confirm this behavior. FEA showed highest strain energy (Delta SED) density per test cycle as BMR reached 80 % and 30 % at the package side and PCB side respectively. The results suggest optimal BMR range as between 50 % and 70 %. Solder paste volume and package surface finish also showed significant impact on TC performance. As solder paste-to-ball volume ratio increased from 35 % to 50 %, more stable wetting occurred on PCB pad and TC lifetime improved by 40 %. Also electrolytic Ni/Au finish showed 30 % higher TC lifetime compared to Cu/ OSP as Ni/ Au increased solder joint hardness.
引用
收藏
页码:656 / 660
页数:5
相关论文
共 50 条
  • [21] SOLDER JOINT RELIABILITY OF FINE PITCH SURFACE MOUNT TECHNOLOGY ASSEMBLIES
    LAU, J
    POWERS, L
    BAKER, J
    RICE, D
    SHAW, B
    SEVENTH IEEE/CHMT INTERNATIONAL ELECTRONIC MANUFACTURING TECHNOLOGY SYMPOSIUM: INTEGRATION OF THE MANUFACTURING FLOW - FROM RAW MATERIAL THROUGH SYSTEMS-LEVEL ASSEMBLY, 1989, : 48 - 60
  • [22] SOLDER JOINT RELIABILITY OF FINE PITCH SURFACE MOUNT TECHNOLOGY ASSEMBLIES
    LAU, J
    POWERSMALONEY, LM
    BAKER, JR
    RICE, D
    SHAW, B
    IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY, 1990, 13 (03): : 534 - 544
  • [23] Board Level Reliability of Solder Joint with a Low CTE PCB
    Harr, Kyoungmoo
    Lee, Chang-Bae
    Kim, Yoon-Su
    Park, Seungwook
    Kim, Jin-Gu
    Kweon, Youngdo
    CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2012 (CSTIC 2012), 2012, 44 (01): : 975 - 983
  • [24] Board Level Reliability of Wafer Level Chip Scale Packages With Copper Post Technology
    Jacobe, April B.
    Lomibao, Pinky B.
    Jackson, John
    IEMT 2006: 31ST INTERNATIONAL CONFERENCE ON ELECTRONICS MANUFACTURING AND TECHNOLOGY, 2006, : 155 - 161
  • [25] Impact of fatigue modeling on 2nd level joint reliability of BGA packages with SnAgCu solder balls
    Stoeckl, S
    Yeo, A
    Lee, C
    Pape, H
    PROCEEDINGS OF THE 7TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS. 1 AND 2, 2005, : 857 - 862
  • [26] Study on the board-level SMT assembly and solder joint reliability of different QFN packages
    Sun, Wei
    Zhu, W. H.
    Danny, Retuta
    Che, F. X.
    Wang, C. K.
    Sun, Anthony Y. S.
    Tan, H. B.
    EUROSIME 2007: THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICRO-ELECTRONICS AND MICRO-SYSTEMS, PROCEEDINGS, 2007, : 344 - +
  • [27] Comprehensive design analysis of QFN and PowerQFN packages for enhanced board level solder joint reliability
    Tee, TY
    Ng, HS
    Diot, JL
    52ND ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2002 PROCEEDINGS, 2002, : 985 - 991
  • [28] Comprehensive board-level solder joint reliability modeling and testing of QFN and PowerQFN packages
    Tee, TY
    Ng, HS
    Yap, D
    Zhong, ZW
    MICROELECTRONICS RELIABILITY, 2003, 43 (08) : 1329 - 1338
  • [29] Effects of Corner and Edgebond Epoxy Adhesives on Board Level Solder Joint Reliability of BGA Mezzanine Connectors
    Song, Fubin
    Yang, Chaoran
    Wu, H. L. Henry
    Lo, C. C. Jeffery
    Lee, S. W. Ricky
    Newman, Keith
    2010 PROCEEDINGS 60TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2010, : 926 - 934
  • [30] Board Level Reliability assessment of Wafer Level Chip Scale Packages for SACQ, a lead-free solder with a novel life prediction model
    Muthuraman, Balaji Nandhivaram
    Canete, Baltazar
    2018 7TH ELECTRONIC SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE (ESTC), 2018,