High-Precision Time-to-Digital Conversion for Calibration of Outphasing Radio Transmitters

被引:0
|
作者
Boopathy, Dhanashree [1 ]
Cheung, Tze Hin [1 ]
Spelman, Andrei [1 ]
Ghosh, Agnimesh [1 ]
Lampu, Vesa [2 ]
Anttila, Lauri [2 ]
Stadius, Kari [1 ]
Kosunen, Marko [1 ]
Ryynanen, Jussi [1 ]
Unnikrishnan, Vishnu [2 ]
机构
[1] Aalto Univ, Dept Elect & Nanoengn, Espoo, Finland
[2] Tampere Univ, Dept Elect Engn, Tampere, Finland
基金
欧盟地平线“2020”; 芬兰科学院;
关键词
quantization; time-to-digital converter (TDC); delay measurement; random sampling; digital circuit; PHASE MODULATOR;
D O I
10.1109/NEWCAS57931.2023.10198030
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Wireless transceivers for 5G NR FR2 frequencies around 30 GHz support signal bandwidths up to 400 MHz to achieve ambitious data rates. The Phase Modulators (PMs) in the FR2 outphasing transmitters generates delays with delay steps of about a few hundred femtoseconds. To calibrate and linearize the PMs, time-to-digital converters (TDCs) that measure delays with higher accuracy in the order of a few femtoseconds are required. To this end, this work explores two synthesizable time interval averaging (TIA) TDCs which employ averaging to achieve a high accuracy with low-precision hardware. The results show that the delay quantization step of the converter has an effect only on the time taken to achieve the required accuracy, presenting opportunities to reduce area and power consumption. Simulation shows that a TDC with quantization step of 12.5 ns achieves an accuracy of 0.3 fs by averaging 228 samples. For a 32 GHz 7-bit PM producing a minimum delay step of 244 fs, this implies a TDC of 8-bit precision for each time step. The hardware synthesized towards a 22nm FDSOI process occupies 0.0004mm(2) area and consumes 0.3mW power.
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页数:5
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