Efficient Test Chip Design via Smart Computation

Competitive strength in semiconductor field depends on yield. The challenges associated with designing and manufacturing of leading-edge integrated circuits (ICs) have increased that reduce yield. Test chips, especially full-flow logic test chips, are increasingly employed to investigate the complex interaction between layout features and the process that improves the total process quality before and during initial mass production. However, designing a high-quality full-flow logic test chip can be time-consuming due to the huge design space and complex process to search for optimal result. This work describes a new design flow that significantly accelerates the logic test chip design process. First, we deploy random forest classification technique to predict potential synthesis outcome for test chip design exploration. Next, a new method is described to efficiently solve the integer programming problem involved in the design process. Various experiments with industrial design have demonstrated that the proposed two methods greatly improve the design efficiency.