GNNHLS: Evaluating Graph Neural Network Inference via High-Level Synthesis

被引:2
|
作者
Zhao, Chenfeng [1 ]
Dong, Zehao [1 ]
Chen, Yixin [1 ]
Zhang, Xuan [1 ]
Chamberlain, Roger D. [1 ]
机构
[1] Washington Univ, McKelvey Sch Engn, St Louis, MO 63110 USA
关键词
field-programmable gate arrays; graph neural networks; high-level synthesis;
D O I
10.1109/ICCD58817.2023.00092
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We present GNNHLS, an open-source framework to comprehensively evaluate GNN inference acceleration on FPGAs via HLS, containing a software stack for data generation and baseline deployment and FPGA implementations of 6 well-tuned GNN HLS kernels. Evaluating on 4 graph datasets with distinct topologies and scales, the results show that GNNHLS achieves up to 50.8x speedup and 423x energy reduction relative to the CPU baselines. Compared with the GPU baselines, GNNHLS achieves up to 5.16x speedup and 74.5x energy reduction.
引用
收藏
页码:574 / 577
页数:4
相关论文
共 50 条
  • [31] Svelto: High-Level Synthesis of Multi-Threaded Accelerators for Graph Analytics
    Minutoli, Marco
    Castellana, Vito Giovanni
    Saporetti, Nicola
    Devecchi, Stefano
    Lattuada, Marco
    Fezzardi, Pietro
    Tumeo, Antonino
    Ferrandi, Fabrizio
    IEEE TRANSACTIONS ON COMPUTERS, 2022, 71 (03) : 520 - 533
  • [32] Dependency Graph-based High-level Synthesis for Maximum Instruction Parallelism
    Gu, Zhenghua
    Wan, Wenqing
    Xie, Jundong
    Wu, Chang
    ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, 2021, 14 (04)
  • [33] Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-level Synthesis
    Oppermann, Julian
    Reuter-Oppermann, Melanie
    Sommer, Lukas
    Sinnen, Oliver
    Koch, Andreas
    2018 28TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL), 2018, : 280 - 286
  • [34] SetCoLa: High-Level Constraints for Graph Layout
    Hoffswell, Jane
    Borning, Alan
    Heer, Jeffrey
    COMPUTER GRAPHICS FORUM, 2018, 37 (03) : 537 - 548
  • [35] A Parametrizable High-Level Synthesis Library for Accelerating Neural Networks on FPGAs
    Kalms, Lester
    Rad, Pedram Amini
    Ali, Muhammad
    Iskander, Arsany
    Goehringer, Diana
    JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2021, 93 (05): : 513 - 529
  • [36] ASNet: Introducing Approximate Hardware to High-Level Synthesis of Neural Networks
    Froehlich, Saman
    Klemmer, Lucas
    Grosse, Daniel
    Drechsler, Rolf
    2020 IEEE 50TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2020), 2020, : 64 - 69
  • [37] A Parametrizable High-Level Synthesis Library for Accelerating Neural Networks on FPGAs
    Lester Kalms
    Pedram Amini Rad
    Muhammad Ali
    Arsany Iskander
    Diana Göhringer
    Journal of Signal Processing Systems, 2021, 93 : 513 - 529
  • [38] Neural Mechanisms of High-Level Vision
    Hegde, Jay
    COMPREHENSIVE PHYSIOLOGY, 2018, 8 (03) : 903 - 953
  • [39] Validating High-Level Synthesis
    Kundu, Sudipta
    Lerner, Sorin
    Gupta, Rajesh
    COMPUTER AIDED VERIFICATION, 2008, 5123 : 459 - 472
  • [40] OPTIMIZATIONS IN HIGH-LEVEL SYNTHESIS
    ROSENSTIEL, W
    MICROPROCESSING AND MICROPROGRAMMING, 1986, 18 (1-5): : 347 - 352