GNNHLS: Evaluating Graph Neural Network Inference via High-Level Synthesis

被引：2

作者：

Zhao, Chenfeng ^{[1
]}

Dong, Zehao ^{[1
]}

Chen, Yixin ^{[1
]}

Zhang, Xuan ^{[1
]}

Chamberlain, Roger D. ^{[1
]}

机构：

[1] Washington Univ, McKelvey Sch Engn, St Louis, MO 63110 USA

来源：

2023 IEEE 41ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, ICCD | 2023年

关键词：

field-programmable gate arrays; graph neural networks; high-level synthesis;

D O I：

10.1109/ICCD58817.2023.00092

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present GNNHLS, an open-source framework to comprehensively evaluate GNN inference acceleration on FPGAs via HLS, containing a software stack for data generation and baseline deployment and FPGA implementations of 6 well-tuned GNN HLS kernels. Evaluating on 4 graph datasets with distinct topologies and scales, the results show that GNNHLS achieves up to 50.8x speedup and 423x energy reduction relative to the CPU baselines. Compared with the GPU baselines, GNNHLS achieves up to 5.16x speedup and 74.5x energy reduction.

引用

页码：574 / 577

页数：4

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