A digital delay locked loop with a monotonic delay line

被引：0
|
作者：
Liu, Jen-Chieh [1 ]
Yang, Chuan [1 ]
机构：
[1] Natl United Univ, Dept Elect Engn, Miaoli, Taiwan
来源：
ELECTRONICS LETTERS | 2023年 / 59卷 / 11期
关键词：
clocks; integrated circuits; digital integrated circuits;
D O I：
10.1049/ell2.12837
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper proposes a digital delay locked loop (DLL) with a monotonic delay line (DL). This DLL adopts the calibration mode to reduce the non-monotonic effects for the coarse-tuning delay line (CTDL) and the fine-tuning delay line (FTDL). The calibration mode detects the delay time of the delay unit, the timing resolution of CTDL, to adjust the delay range of the FTDL. Thus, the calibration mode can limit the overlap range of the delay time between the CTDL and the FTDL. The proposed DLL was implemented using a 0.18-mu m CMOS process, and the RMS and the peak-to-peak jitters of the DLL were 0.21% and 1.72%, respectively, at 560 MHz.
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页数：3
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