A Resolution-Tunable Low Power Time-to-Digital Converter With an Improved ADDLL Based on a Cyclic Pulse Ring Oscillator

This article presents a resolution-tunable time-to-digital converter (TDC) with a three-level structure, in which the low-level TDC employs an improved all-digital delay-locked loop (ADDLL) based on a cyclic pulse ring oscillator (CPRO) and a digital controller for detection lock state (DLS). Specifically, a bidirectional bypass transmission delay unit (BBTDU) in CPRO provides adjustable resolution with a 15 ps coarse delay step and a 3.5 ps fine delay step. Second, a data processing approach is presented to open the window to extract a 4-bit binary data of the bidirectional serial shift register line (BSSRL) in ADDLL for DLS and update the values of BSSRL at the same position of windowing, which can reduce the number of manipulated registers in BSSRL by approximately 93.7%. Then, a methodology of detecting the locking pattern between lock and unlock and selecting the fixed optimal windowing sequence to update the controlling values of BSSRL is proposed to eliminate dithering in a locked state, which can reduce the clock phase jitter when locked. Finally, the proposed TDC has been integrated into a system-on-chip (SoC) and fabricated in 65-nm CMOS technology. The measurement results implemented with a 30 MHz reference clock demonstrate that a resolution-tunable TDC with low power has been obtained. There are six configurable resolutions in all. When configured to a minimum resolution of 7.78 ps, the power consumption and the precision are 4.812 mW and 3.02 ps, respectively. While configured for a maximum resolution of 29.7 ps, the power consumption and the precision are 2.874 mW and 13.2 ps, respectively. The proposed TDC is extremely flexible and well-suited for integration into other large-scale application-specific integrated circuit (ASIC) chips to extend the application range, especially for low-frequency applications.