Impact of the channel doping on the low-frequency noise of gate-all-around silicon vertical nanowire pMOSFETs

被引：2

作者：

Simoen, Eddy ^{[1
]}

Veloso, Anabela ^{[2
]}

Matagne, Philippe ^{[2
]}

Claeys, Cor ^{[3
]}

机构：

[1] Univ Ghent, Dept Solid State Sci, Krijgslaan 281-S1, B-9000 Ghent, Belgium

[2] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

[3] ClaRoo Consulting, Leuven, Belgium

来源：

SOLID-STATE ELECTRONICS | 2023年 / 200卷

关键词：

Silicon nanowires; SOI; Low-frequency noise; Nanowire doping;

D O I：

10.1016/j.sse.2022.108576

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work, the impact of the channel doping density on the low-frequency noise of silicon Gate-All-Around (GAA) Vertical Nanowire (VNW) pMOSFETs on Silicon-on-Insulator (SOI) substrates will be described and discussed. It is demonstrated that the dominant fluctuation mechanism of the 1/f noise in the subthreshold regime changes from number (& UDelta;n) to mobility (& UDelta;& mu;) fluctuations with increasing p-type doping density of the silicon nanowires. At the same time, the lowest input-referred voltage noise Power Spectral Density is observed for an intermediate boron concentration in the nanowire of 5 x 1018 cm-3.

引用

页数：6

共 50 条

[31] Channel size dependence of low-frequency noise in tri-gate silicon nanowire transistors
Saitoh, Masumi
Ota, Kensuke
Tanaka, Chika
Numata, Toshinori
[J]. JAPANESE JOURNAL OF APPLIED PHYSICS, 2015, 54 (04)
[32] High-Performance Vertical Gate-All-Around Silicon Nanowire FET With High-κ/Metal Gate
Zhai, Yujia
Mathew, Leo
Rao, Rajesh
Palard, Marylene
Chopra, Sonali
Ekerdt, John G.
Register, Leonard F.
Banerjee, Sanjay K.
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (11) : 3896 - 3900
[33] Simulation of flicker noise in gate-all-around Silicon Nanowire MOSFETs including interface traps
Anandan, P.
Nithya, A.
Mohankumar, N.
[J]. MICROELECTRONICS RELIABILITY, 2014, 54 (12) : 2723 - 2727
[34] High-Frequency Gate-All-Around Vertical InAs Nanowire MOSFETs on Si Substrates
Johansson, Sofia
Memisevic, Elvedin
Wernersson, Lars-Erik
Lind, Erik
[J]. IEEE ELECTRON DEVICE LETTERS, 2014, 35 (05) : 518 - 520
[35] Characteristics of gate-all-around silicon nanowire field effect transistors with asymmetric channel width and source/drain doping concentration
Beek, Chang-Ki
Park, Sooyoung
Ko, Myung-Dong
Rim, Taiuk
Choi, Seongwook
Jeong, Yoon-Ha
[J]. JOURNAL OF APPLIED PHYSICS, 2012, 112 (03)
[36] Nonvolatile operation of vertical ferroelectric gate-all-around nanowire transistors
Fujisawa, Hironori
Ikeda, Kazuma
Nakashima, Seiji
[J]. JAPANESE JOURNAL OF APPLIED PHYSICS, 2021, 60 (SF)
[37] 1/f Noise in 3D Vertical Gate-all-around Junction-less Silicon Nanowire Transistors
Mukherjee, Chhandak
Maneux, Cristell
Pezard, Julien
Larrieu, Guilhem
[J]. 2017 47TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 2017, : 34 - 37
[38] DC AND LOW-FREQUENCY NOISE CHARACTERISTICS OF GAMMA-IRRADIATED GATE-ALL-AROUND SILICON-ON-INSULATOR MOS-TRANSISTORS
SIMOEN, E
CLAEYS, C
COENEN, S
DECRETON, M
[J]. SOLID-STATE ELECTRONICS, 1995, 38 (01) : 1 - 8
[39] Impact of Silicon Body Thickness on the Performance of Gate-all-around Silicon nanowire field effect transistor
Gupta, Richa
Dass, Devi
Prasher, Rakesh
Vaid, Rakesh
[J]. PHYSICS OF SEMICONDUCTOR DEVICES, 2014, : 689 - 692
[40] In-depth static and low frequency noise assessment of p-channel gate-all-around vertically stacked silicon nanosheets
Cretu, B.
Veloso, A.
Simoen, E.
[J]. SOLID-STATE ELECTRONICS, 2023, 201

← 1 2 3 4 5 →