Efficient multi-level fault simulation of HW/SW systems for structural faults

In recent technology nodes,reliability is increasingly considered a part of the standard design flow to be taken into account at all levels of embedded systems design.While traditional fault simulation techniques based on low-level models at gate-and register transfer-level offer high accuracy,they are too inefficient to properly cope with the complexity of modern embedded systems.Moreover,they do not allow for early exploration of design alternatives when a detailed model of the whole system is not yet available,which is highly required to increase the efficiency and quality of the design flow.Multi-level models that combine the simulation efficiency of high abstraction models with the accuracy of low-level models are therefore essential to efficiently evaluate the impact of physical defects on the system.This paper proposes a methodology to efficiently implement concurrent multi-level fault simulation across gate-and transaction-level models in an integrated simulation environment.It leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction-level modeling.This combination of different models allows to accurately evaluate the impact of faults on the entire hardware/software system while keeping the computational effort low.Moreover,since only selected portions of the system require low-level models,early exploration of different design alternatives is efficiently supported.Experimental results obtained from three case studies are presented to demonstrate the high accuracy of the proposed method when compared with a standard gate/RT mixed-level approach and the strong improvement of simulation time which is reduced by four orders of magnitude in average.