Device parameter optimization for sub-20nm node HK/MG-last bulk FinFETs

被引：0

作者：

许淼 ^{[1
]}

殷华湘 ^{[1
]}

朱慧珑 ^{[1
]}

马小龙 ^{[1
]}

徐唯佳 ^{[1
]}

张永奎 ^{[1
]}

赵治国 ^{[1
]}

罗军 ^{[1
]}

杨红 ^{[1
]}

李春龙 ^{[1
]}

孟令款 ^{[1
]}

洪培真 ^{[1
]}

项金娟 ^{[1
]}

高建峰 ^{[1
]}

徐强 ^{[1
]}

熊文娟 ^{[1
]}

王大海 ^{[1
]}

李俊峰 ^{[1
]}

赵超 ^{[1
]}

陈大鹏 ^{[1
]}

杨士宁 ^{[1
]}

叶甜春 ^{[1
]}

机构：

[1] Key Laboratory of Microelectronics Devices and Integrated Technology,Institute of Microelectronics,Chinese Academy of Sciences

来源：

Journal of Semiconductors | 2015年 / 04期

关键词：

bulk FinFET; effective work function(EWF); extension thermal budget; metal gate;

D O I：

暂无

中图分类号：

TN386 [场效应器件];

学科分类号：

摘要：

Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate(HK/MG) process are fabricated and the influence of a series of device parameters on the device scaling is investigated.The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure.The punch through stop layer(PTSL) and source drain extension(SDE) doping profiles are carefully optimized.The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation.The band-edged MG has a better short channel effect immunity,but the lower effective work function(EWF) MG shows a larger driveability.A tradeoff choice for different EWF MGs should be carefully designed for the device’s scaling.

引用

页码：70 / 73

页数：4

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