Device to circuit level implementation of JL-NSFET for DC/analog/RF applications at sub-5nm technology node: design optimization and temperature analysis

This manuscript introduces, for the first time, a novel approach that incorporates a comprehensive analysis of sheet variations (1-5) and every individual sheet wise temperature variation, and as well as an investigation of various GS high-k gate dielectrics in Junction-less (JL) Nanosheet FET (JL-NSFET). The study starting from device level (Digital/Analog/Radio Frequency) to circuit (CMOS Inverter and ring oscillator) as a whole package is investigated through well calibrated TCAD simulation and the results portrayed. NSFETs are the ultimate choice for integrated circuits (ICs) at sub-5 nm technology node. The notion of this paper is to design and optimization of NSFET with GS high-k gate dielectrics (Al2O3, HfO2, ZrO2 and TiO2) Initially. The switching/analog and RF metric revels that HfO2 is superior in terms SS, switching applications and more compactable with CMOS process. Further, adding number of sheets and temperature variation has been done later. As number of sheets increases, the effective channel width increases, electric field distribution takes place evenly and enhanced gate control owing to improved I-ON, I-ON/I(OFF )ratio, SS and DIBL. However, increasing the number of vertical channel layers (sheets) more than 2 results into diminished analog/RF performance of JL-NSFET owing to increased parasitic capacitances. Further, the impact of temperature variations (250 K to 450 K) studied for different sheet variations (1 to 5) and noticed that analog/RF such as g(m), g(ds), f(T), TFP and GTFP are enhanced by 40.82%, 28.76%, 40.69%, 64.62% and 70.59%, respectively at lower temperature (250 K) when compared to high temperature (450 K). These enhancements make the device is ideal for applications in cryogenic computing systems, satellites, deep space probes, and other aerospace technologies. Furthermore, as the circuit level implementation CMOS inverter and 5-stage ring oscillator (RO) are examined for different sheets and observed as sheets increase delay and EDP increases. For a CMOS inverter the NMH (0.295 V) and NML (0.280 V) are better at 2 sheets with a highest gain of 9.38 V/V. Hence, it is advised to use two or three sheets-based JL-NSFETs for high-performance and lower-power analog/RF applications.