An IP-oriented 11-bit 160 MS/s 2-channel current-steering DAC

This paper presents an 11-bit 160 MS/s 2-channel current-steering digital-to-analog converter(DAC)IP. The circuit and layout are carefully designed to optimize its performance and area. A 6-2-3 segmented structure is used for the trade-off among linearity, area and layout complexity. The sizes of current source transistors are calculated out according to the process matching parameter. The unary current cells are placed in a one-dimension distribution to simplify the layout routing, spare area and wiring layer. Their sequences are also carefully designed to reduce integral nonlinearity. The test result presents an SFDR of 72 dBc at 4.88 MHz input signal with DNL 60.25 LSB, INL 6 0.8 LSB. The full-scale output current is 5 m A with a 2.5 V analog power supply. The core of each channel occupies 0.08 mm2 in a 1P-8M 55 nm CMOS process.