Analysis of the dV/dt effect on an IGBT gate circuit in IPM

被引:0
|
作者
华庆 [1 ]
李泽宏 [1 ]
张波 [1 ]
黄祥钧 [2 ]
程德凯 [2 ]
机构
[1] State Key Laboratory of Electronic Thin Films and Integrated Devices,University of Electronic Science and Technology of China
[2] Midea Air-Conditioning & Refrigeration Research Institute
关键词
IGBT; dV/dt; voltage spike; IPM;
D O I
暂无
中图分类号
TN322.8 [];
学科分类号
摘要
The effect of dV/dt on the IGBT gate circuit in IPM is analyzed both by simulation and experiment.It is shown that a voltage slope applied across the collector-emitter terminals of the IGBT can induce a gate voltage spike through the feedback action of the parasitic capacitances of the IGBT.The dV/dt rate,gate-collector capacitance, gate-emitter capacitance and gate resistance have a direct influence on this voltage spike.The device with a higher dV/dt rate,gate-collector capacitance,gate resistance and lower gate-emitter capacitance is more prone to dV/dt induced self turn-on.By optimizing these parameters,the dV/dt induced voltage spike can be effectively controlled.
引用
收藏
页码:64 / 68
页数:5
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