Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example

This paper makes a review of state-of-thearts designs of successive-approximation register analog-to-digital converters(SAR ADCs).Methods and technique specifications are collected in view of innovative ideas.At the end of this paper,a design example is given to illustrate the procedure to design an SAR ADC.A new method,which extends the width of the internal clock,is also proposed to facilitate different sampling frequencies,which provides more time for the digital-to-analog convert(DAC)and comparator to settle.The 10 bit ADC is simulated in 0.13 m CMOS process technology.The signal-to-noise and distortion ratio(SNDR)is 54.41 dB at a 10 MHz input with a 50MS/s sampling rate,and the power is 330 W.