A Subcircuit Matching Approach to Structural Analog Circuit Model Generation and Sizing

In this paper we study an application of Ohlrich's SubGemini algorithm, a subcircuit matching algorithm, to structural modeling and sizing of CMOS analog integrated circuits with emphasis on multiple-stage circuits including Op Amps and low-dropout (LDO) regulators. Structural modeling can help the design of multiple-stage circuits by introducing structural reduction, structural constraint, and structural mapping, enabling design automation in this field with a traceable circuit manipulation track. Given the fact that a large number of CMOS transistor-level components (cells) are frequently used in analog integrated circuit, we propose to create a library for such commonly used cells and develop a hierarchical subcircuit matching engine (by an adaptation of the SubGemini algorithm) to decompose structurally an analog circuit into a cell form assembly. This work can also be considered a structural circuit recognition work, which can be applied to fast macromodel generation and sizing constraint generation. Procedural details are presented and applications are demonstrated.