CiMComp: An Energy Efficient Compute-in-Memory based Comparator for Convolutional Neural Networks

被引:0
|
作者
Kavitha, S. [1 ]
Kailath, Binsu J. [1 ]
Reniwal, B. S. [2 ]
机构
[1] IIITDM Kancheepuram, Indian Inst Informat Technol Design & Mfg, Chennai, Tamil Nadu, India
[2] Indian Inst Thchnol, Jodhpur, Rajasthan, India
来源
2024 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE | 2024年
关键词
SRAM; In memory computing (IMC); XOR; Subtractor; Comparator;
D O I
10.23919/DATE58400.2024.10546864
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The utilization of large datasets in applications results in significant energy expenditures attributed to frequent data shifts between memory and processing units. In-Memory Computing (IMC) distinguishes itself by employing computations within a memory crossbar to perform logic operations, leading to enhanced computational speed and energy efficiency. This study introduces RASA-based subtractor, strategically improved for computation, and energy consumption. Subsequently, the proposed subtractor are employed to construct a comparator and facilitate pooling operations. The comparator is developed using the proposed subtractor, achieves the comparison in n steps for a n-bit comparator. Additionally, a n-bit min pooling operation for anxn (4 x 4) feature map requires 2-1 (15) steps. Energy consumption of the RASA design demonstrates hopped up performance, showcasing an average savings of 87.42% and 89.98% compared to the ASA and Muller C based subtractor.
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收藏
页数:2
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