Single-Ended/Differential Wideband Track-and-Hold Amplifier in 22-nm FD-SOI CMOS Process

The impending 6G communication based on the software defined radio (SDR) requires a radio frequency (RF) track-and-hold amplifier (THA). This THA serves as the frequency down-converter and the single-to-differential interface to the downstream analog-to-digital converter (ADC). We present a CMOS RF THA that features wide and width (18 GHz), yet high linearity (spurious free dynamic range (SFDR) of 56.7 dB) and not requiring an external balun. These features are derived from our proposed isolation technique based on our proposed double source follower enhanced (DSFE) structure. To realize the single-to-differential conversion without an external balun, we design an independent balun as the first stage. Thereafter, we employ our proposed feedforward compensation technique (FCT) along with the reported phase correction technique (PCT) to reduce the output mismatches while simultaneously enhancing the linearity and bandwidth. We monolithically realize the RF THA in 22-nm fully-depleted silicon-on-insulator (FD-SOI) CMOS operating at 1.8 V. Measurements depict that the input bandwidth is wide (18 GHz), yet featuring high linearity (SFDR = 56.7 dB at 15 GHz) with 2 GS/s sampling rate. The power consumption and the chip area are low and small at 216 mW and 0.07 mm(2) , respectively. When benchmarked against reported III/V RF THAs, the proposed CMOS RF THA is very competitive-comparable bandwidth, yet simultaneously higher linearity, potentially lower cost, lower power dissipation, and smaller die area. Further because it is realized in CMOS, it facilitates integration to other CMOS circuits in the same system-on-chip (SoC).