Automated Matching Placement Generation in Analog Circuits

The layout of matching devices is crucial in analog circuit design as it impacts matching, parasitic effects, and performance. Common-centroid layout, a popular method, minimizes mismatches but designing an efficient algorithm is challenging. This paper introduces a comprehensive automated matching placement algorithm for analog circuits, optimizing both common-centroid requirements and device positions to enhance accuracy and minimize area. Under the premise of minimizing performance degradation, we implemented a fully automated process from netlist to final design, demonstrating effective matching placement for transistor arrays in differential pairs and current mirrors, significantly reducing layout area and parasitic effects.