Scatterometry measurement of sub-0.1 μm linewidth gratings

被引：0
|
作者：
Coulombe, Stephen A.
Minhas, Babar K.
Raymond, Christopher J.
Naqvi, S. Sohail H.
McNeil, John R.
机构：
来源：
Journal of Vacuum Science & Technology B: Microelectronics Processing and Phenomena | 1998年 / 16卷 / 01期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [41] Low temperature operation of ultra-thin gate oxide sub-0.1 μm MOSFETs
    Cretu, B
    Balestra, F
    Ghibaudo, G
    Guégan, G
    JOURNAL DE PHYSIQUE IV, 2002, 12 (PR3): : 57 - 60
  • [42] Improvement of electrical properties in sub-0.1 μm MOSFETs with a novel shallow trench isolation structure
    Eom, GY
    Oh, HS
    JOURNAL OF THE KOREAN PHYSICAL SOCIETY, 2003, 43 (01) : 102 - 104
  • [43] Reliable and enhanced performances of sub-0.1 μm pMOSFETs doped by low biased Plasma Doping
    Lenoble, D
    Arnaud, F
    Grouillet, A
    Liebert, R
    Walther, S
    Felch, SB
    Fang, Z
    Haond, M
    2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, : 110 - 111
  • [44] Effect of the transient enhanced diffusion of boron on the characteristics of sub-0.1 μm n-MOSFETS
    Kumashiro, S
    MATERIALS SCIENCE AND ENGINEERING B-SOLID STATE MATERIALS FOR ADVANCED TECHNOLOGY, 2000, 71 : 148 - 154
  • [45] Sub-0.1 μm nitride hard mask open process without precuring the ArF photoresist
    Kim, J
    Chae, YS
    Lee, WS
    Shon, JW
    Kang, CJ
    Han, WS
    Moon, JT
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2003, 21 (02): : 790 - 794
  • [46] Impact of gate current on first order parameter extraction in Sub-0.1 μm CMOS technologies
    Planes, N
    Dray, A
    Robilliart, E
    Brut, H
    ICMTS 2003: PROCEEDINGS OF THE 2003 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, 2003, : 137 - 141
  • [47] Silicon resonant tunneling metal-oxide-semiconductor transistor for sub-0.1 μm era
    Matsuo, N
    Takami, Y
    Nozaki, T
    Hamada, H
    IEICE TRANSACTIONS ON ELECTRONICS, 2002, E85C (05) : 1086 - 1090
  • [48] Insight into the relationship between hot electron degradation and substrate current in sub-0.1 μm technologies
    Ghetti, A
    Bude, J
    Liu, CT
    SOLID-STATE ELECTRONICS, 2001, 45 (09) : 1591 - 1595
  • [49] Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs:: optimization of the device architecture
    Ernst, T
    Tinella, C
    Raynaud, C
    Cristoloveanu, S
    SOLID-STATE ELECTRONICS, 2002, 46 (03) : 373 - 378
  • [50] Shallow source/drain extension effects on external resistance in sub-0.1 μm MOSFET's
    Choi, CH
    Goo, JS
    Yu, ZP
    Dutton, RW
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2000, 47 (03) : 655 - 658
12345