Ultra-thin Strained-SOI CMOS for High Temperature Operation

被引:0
|
作者
机构
[1] Maeda, T.
[2] Mizuno, T.
[3] Sugiyama, N.
[4] Tezuka, T.
[5] Numata, T.
[6] Koga, J.
[7] Takagi, S.
来源
Maeda, T. (t-maeda@aist.go.jp) | 1600年 / Institute of Electrical and Electronics Engineers Inc.期
关键词
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
相关论文
共 50 条
  • [21] Ultra-thin gate oxide technology for high performance CMOS
    Momose, HS
    Nakamura, S
    Katsumata, Y
    Iwai, H
    ULSI SCIENCE AND TECHNOLOGY / 1997: PROCEEDINGS OF THE SIXTH INTERNATIONAL SYMPOSIUM ON ULTRALARGE SCALE INTEGRATION SCIENCE AND TECHNOLOGY, 1997, 1997 (03): : 235 - 246
  • [22] Transport study of ultra-thin SOI MOSFETs
    Naser, B
    Cho, KH
    Hwang, SW
    Bird, JP
    Ferry, DK
    Goodnick, SM
    Park, BG
    Ahn, D
    PHYSICA E-LOW-DIMENSIONAL SYSTEMS & NANOSTRUCTURES, 2003, 19 (1-2): : 39 - 43
  • [23] Fabrication of ultra-thin strained silicon on insulator
    Drake, TS
    Ní Chléirigh, C
    Lee, ML
    Pitera, AJ
    Fitzgerald, EA
    Antoniadis, DA
    Anjum, DH
    Li, J
    Hull, R
    Klymko, N
    Hoyt, JL
    JOURNAL OF ELECTRONIC MATERIALS, 2003, 32 (09) : 972 - 975
  • [24] Fabrication of ultra-thin strained silicon on insulator
    T. S. Drake
    C. Ní Chléirigh
    M. L. Lee
    A. J. Pitera
    E. A. Fitzgerald
    D. A. Antoniadis
    D. H. Anjum
    J. Li
    R. Hull
    N. Klymko
    J. L. Hoyt
    Journal of Electronic Materials, 2003, 32 : 972 - 975
  • [25] Thermal scaling of ultra-thin SOI: Reduced resistance at low temperature RTA
    Yang, JH
    Oh, J
    Im, K
    Baek, IB
    Ahn, CG
    Park, J
    Cho, WJ
    Lee, S
    ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2004, : 153 - 156
  • [26] Control of threshold-voltage and short-channel effects in ultrathin strained-SOI CMOS devices
    Numata, T
    Mizuno, T
    Tezuka, T
    Koga, J
    Takagi, S
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (08) : 1780 - 1786
  • [27] Power-gating schemes for ultra-thin SOI (UTSOI) circuits in hybrid SOI-epitaxial CMOS structures
    Lo, Shih-Hsien
    Das, Koushik K.
    Chuang, Ching-Te
    Sleight, Jeffrey W.
    2006 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PAPERS, 2006, : 49 - +
  • [28] Channel-drain lateral profile engineering for advanced CMOS on ultra-thin SOI technology
    Adan, AO
    Kaneko, S
    Naka, T
    Urabe, D
    Higashi, K
    Kagisawa, A
    1996 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS, 1996, : 100 - 101
  • [29] High performance and highly stable ultra-thin oxynitride for CMOS applications
    Zhu, Wenjuan
    Shepard, Joseph
    He, Wei
    Ray, Asit
    Ronsheim, Paul
    Schepis, Dominic
    Mocuta, Dan
    Leobandung, Effendi
    2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 223 - 226
  • [30] Design considerations of ultra-thin body SOI MOSFETs
    Tian, Y
    Huang, R
    2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS, 2004, : 283 - 286