Testing VLSI regular arrays

被引：0

作者：

Univ Coll, Cork, Ireland ^{[1
]}

机构：

来源：

J Electron Test Theory Appl JETTA | / 2卷 / 153-177期

关键词：

D O I：

暂无

中图分类号：

学科分类号：

摘要：

引用

共 50 条

[21] TESTING VLSI COMPONENTS
HUTCHESON, JD
SOLID STATE TECHNOLOGY, 1982, 25 (11) : 79 - 79
[22] Testing in VLSI: A Survey
Rinitha, R.
Ponni, R.
FIRST INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ENGINEERING, TECHNOLOGY AND SCIENCE - ICETETS 2016, 2016,
[23] VLSI TESTING AND TESTABILITY
ERENYI, I
MICROPROCESSING AND MICROPROGRAMMING, 1993, 38 (1-5): : 221 - 221
[24] ON THE DESIGN OF ALGORITHMS FOR VLSI SYSTOLIC ARRAYS
MOLDOVAN, DI
PROCEEDINGS OF THE IEEE, 1983, 71 (01) : 113 - 120
[25] Accelerating reconfiguration of degradable VLSI arrays
Wu, J.
Srikanthan, T.
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2006, 153 (04): : 383 - 389
[26] EMBEDDING TERNARY TREES IN VLSI ARRAYS
PINTER, SS
WOLFSTAHL, Y
INFORMATION PROCESSING LETTERS, 1987, 26 (04) : 187 - 191
[27] SORTING ON DEFECTIVE VLSI-ARRAYS
KRAMMER, JG
BERNARD, EG
SAUER, M
NOSSEK, JA
INTEGRATION-THE VLSI JOURNAL, 1991, 12 (01) : 33 - 48
[28] GATE ARRAYS FOR VLSI DESIGN.
Fulkerson, David E.
IEEE transactions on components, hybrids, and manufacturing technology, 1981, CHMT-5 (01): : 133 - 137
[29] On the reconfiguration of degradable VLSI/WSI arrays
Low, CP
Leong, HW
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1997, 16 (10) : 1213 - 1221
[30] RECONFIGURABLE ARCHITECTURES FOR VLSI PROCESSING ARRAYS
SAMI, M
STEFANELLI, R
AFIPS CONFERENCE PROCEEDINGS, 1983, 52 : 565 - &