Optimization of test accesses with a combined BIST and external test scheme

被引:0
|
作者
Sugihara, Makoto [1 ]
Yasuura, Hiroto [1 ]
机构
[1] Dept. of Comp. Sci. and Commun. Eng., Grad. Sch. of Info. Sci. Elec. Eng., Kyushu University, Kasuga-shi, 816-8580, Japan
关键词
D O I
暂无
中图分类号
学科分类号
摘要
10
引用
收藏
页码:2731 / 2738
相关论文
共 50 条
  • [1] Optimization of test accesses with a combined BIST and external test scheme
    Sugihara, M
    Yasuura, H
    ASP-DAC/VLSI DESIGN 2002: 7TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE AND 15TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2002, : 683 - 688
  • [2] Optimization of test accesses with a combined BIST and external test scheme
    Sugihara, M
    Yasuura, H
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2001, E84A (11): : 2731 - 2738
  • [3] Implementation of a BIST scheme for ADC test
    Wu, GL
    Rao, J
    Ren, AL
    Ling, M
    2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 1128 - 1131
  • [4] A Unified DFT Approach for BIST and External Test
    M.-L. Flottes
    C. Landrault
    A. Petitqueux
    Journal of Electronic Testing, 2003, 19 : 49 - 60
  • [5] A unified DFT approach for BIST and external test
    Flottes, ML
    Landrault, C
    Petitqueux, A
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2003, 19 (01): : 49 - 60
  • [6] Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping
    Zhou, Bin
    Xiao, Li-yi
    Ye, Yi-Zheng
    Wu, Xin-Chun
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2011, 27 (01): : 43 - 56
  • [7] Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping
    Bin Zhou
    Li-yi Xiao
    Yi-Zheng Ye
    Xin-Chun Wu
    Journal of Electronic Testing, 2011, 27 : 43 - 56
  • [8] An efficient test pattern generation scheme for an on chip BIST
    Varaprasad, BKSVL
    Patnaik, LM
    Jamadagni, HS
    Agrawal, VK
    VLSI DESIGN, 2001, 12 (04) : 551 - 562
  • [9] An effective BIST scheme for SRAM full speed test
    Zhang, Lijun
    Yu, Yue
    Zheng, Jianbin
    Song, Xiaoyu
    INTERNATIONAL JOURNAL OF ELECTRONICS, 2011, 98 (09) : 1281 - 1290
  • [10] A low cost test pattern generator for test-per-clock BIST scheme
    Lei, Shaochong
    Wang, Zhen
    Liu, Zeye
    Liang, Feng
    IEICE ELECTRONICS EXPRESS, 2010, 7 (10): : 672 - 677