Methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design

被引：0

作者：

Iwabuchi, Masato ^{[1
]}

Sakamoto, Noboru ^{[1
]}

Sekine, Yasushi ^{[1
]}

Omachi, Takashi ^{[1
]}

机构：

[1] Hitachi, Ltd, Tokyo, Japan

来源：

Proceedings of the International Symposium on Physical Design | 1999年

关键词：

D O I：

暂无

中图分类号：

学科分类号：

摘要：

引用

页码：9 / 15

共 50 条

[21] Load-Balanced Clock Tree Synthesis with Adjustable Delay Buffer Insertion for Clock Skew Reduction in Multiple Dynamic Supply Voltage Designs
Lin, Kuan-Yu
Lin, Hong-Ting
Ho, Tsung-Yi
Tsai, Chia-Chun
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2012, 17 (03)
[22] Robust Clock Network Design Methodology for Ultra-Low Voltage Operations
Seok, Mingoo
Blaauw, David
Sylvester, Dennis
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, 2011, 1 (02) : 120 - 130
[23] Useful Clock Skew Scheduling Using Adjustable Delay Buffers in Multi-Power Mode Designs
Kim, Juyeon
Kim, Taewhan
2015 20TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2015, : 466 - 471
[24] New Activity-Driven Clock Tree Design Methodology for Low Power Clock Gating
Lin, Chen-Hsien
Huang, Shih-Hsu
Jian, Jia-Hong
Chen, Xin-Jia
2017 6TH INTERNATIONAL SYMPOSIUM ON NEXT GENERATION ELECTRONICS (ISNE), 2017,
[25] An Enhanced Clock Tree Synthesis Methodology for Optimizing Power in Physical Design
Anirudh, S.
Ramesh, T. K.
2022 IEEE 3RD INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURE, TECHNOLOGY AND APPLICATIONS, VLSI SATA, 2022,
[26] Voltage drop?: concept, causes and effects in an industrial power system
Ruiz Flores, Luis Ivan
2015 IEEE THIRTY FIFTH CENTRAL AMERICAN AND PANAMA CONVENTION (CONCAPAN XXXV), 2015,
[27] A novel methodology for reducing the power supply voltage drop at the core of IC's chips
Abdel-Hafeez, Saleh M.
JOURNAL OF ELECTRICAL ENGINEERING-ELEKTROTECHNICKY CASOPIS, 2007, 58 (03): : 177 - 179
[28] Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits
Zhao, Xin
Tolbert, Jeremy R.
Mukhopadhyay, Saibal
Lim, Sung Kyu
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2012, 31 (08) : 1222 - 1234
[29] Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling
Ahn, Seyong
Kang, Minseok
Papaefthymiou, Marios C.
Kim, Taewhan
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2016, 35 (12) : 2068 - 2081
[30] Design of a low power DSP with distributed and early clock gating
Wang, Bing
Wang, Qin
Peng, Rui-Hua
Fu, Yu-Zhuo
Journal of Shanghai Jiaotong University (Science), 2007, 12 E (05) : 610 - 617

← 1 2 3 4 5 →