Methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design

被引：0
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作者：
Iwabuchi, Masato [1 ]
Sakamoto, Noboru [1 ]
Sekine, Yasushi [1 ]
Omachi, Takashi [1 ]
机构：
[1] Hitachi, Ltd, Tokyo, Japan
来源：
Proceedings of the International Symposium on Physical Design | 1999年
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页码：9 / 15
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